The present invention relates generally to improved fill patterns for semiconductor devices, and more particularly to geometrically simple arrays of fill patterns interspersed among conductive elements to promote the formation of an insulating planarization layer.
The deposition of the numerous layers is one of the key steps in the fabrication of semiconductor devices, where typically alternating patterns of conductive and nonconductive materials are topographically formed on a semiconductor substrate. In a typical photolithographic process, a patterned reticle is employed to provide masking of selected sections of a resist layer on both the semiconductor substrate and subsequent layers, repeated through numerous steps to build a three-dimensional network of connectors. However, the addition of multiple layers causes the topographic projection to become more and more nonplanar; these surface undulations can lead to a loss of resolution in the lithographic masking process.
It is therefore highly desirable from a process and quality control perspective to have as little surface undulation as possible on the built-up semiconductor device. One way to minimize the surface undulation is to planarize each exposed surface with one or more insulative layers using known procedures, such as spin-on glass (SOG) or chemical vapor deposition (CVD) methods. One commonly used material in this CVD process is tetraethylorthosilicate (TEOS). When either of these approaches are used to deposit a layer over large tracts of non built-up area, they tend to produce tapered layer thickness variations near the topographic regions in a manner similar to that of a meniscus formed near a container wall due to surface tension in a liquid. To achieve the desired level of planarization, it is precisely this conformal behavior, prevalent in wide-open areas, that substrate designers have been trying to avoid. Similarly, when spacing widths between the rigid upstanding structures varies, the aforementioned layer fill techniques are less than wholly effective at achieving the desired planarization, as spaces of varying size permit disparate amounts of SOG or TEOS to flow into them, and at different rates.
Additional methods have been employed to improve the planarity of insulative layers. One well-known approach involves the placement of “dummy” or fill patterns in between the topographic conductive elements to reduce the incidence of conformal dips in the insulative layer. The presence of these fill patterns which, by interrupting otherwise large tracts of unsupported fill area, subdivide and create smaller valley- or grid-like regions for SOG or TEOS layers to fill. However, the addition of fill patterns adds complexity, as additional steps must be included to ensure their mechanical and electrical compatibility. For example, since many fill patterns are metal (often deposited simultaneously with the conductive element steps), they can be a source of unwanted conductivity or capacitance. Similarly, a lack of uniformity of spacing between the patterns making up the fill pattern array hampers the even distribution of the layers. The relatively non-uniform spacing between adjacent topographic structures also militates against lower processing costs, where these considerations dictate that fill patterns and the arrays made therefrom be as simple as possible. The cost of depositing customized, non-uniform fill patterns can have a significant impact on fabrication cost; on the other hand, improper attention to a grid or valley layout between fill patterns can lead to spaces that, if inclusive of long straight paths and high throughflow intersections, will exhibit uneven planarization layer flow, and subsequent undulated layer deposition. Accordingly, fill pattern size and spacing become critical design considerations to the person responsible for the circuit layout.
Accordingly, the need exists for devices in which fill patterns can be consistently and substantially planar across the entire region of the upper surface of the semiconductor device to provide inexpensive, compact and reliable structures.